iMACE: In-Memory Acceleration of Classic McEliece Encoder

Abstract

Asymmetric code-based crypto-systems have been developed in the last decade due to rapid evolution of quantum computing that can potentially compromise RSA and ECC based crypto-systems. The McEliece crypto-system based on the general decoding problem is one of the front runner candidates for post-quantum cryptography but the energy-efficiency is limited by the heavy data traffic between the processing elements and the memory. In memory-computing (IMC) architectures can remove the energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as, Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Therefore, McEliece can be benefited substantially by in-memory acceleration. We propose, iMACE, a high performance and area-efficient hardware implementation of the core encoding function of McEliece by exploiting ReRAM-based IMC. Simulation results show 18.8X-94X better throughput and 46%-97% reduction in energy consumption compared to the FPGA-based implementation.