A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS

Xiang Yi, C. Boon, Hang-Ji Liu, Jia-fu Lin, J. Ong, W. M. Lim
{"title":"A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS","authors":"Xiang Yi, C. Boon, Hang-Ji Liu, Jia-fu Lin, J. Ong, W. M. Lim","doi":"10.1109/ISSCC.2013.6487767","DOIUrl":null,"url":null,"abstract":"Under the influence of increasing demand for high-data-rate communication systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz frequency synthesizer, which employs an in-phase injection-coupled QVCO (IPIC-QVCO) to produce low-phase-noise quadrature signals with low power.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2013.6487767","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 35

Abstract

Under the influence of increasing demand for high-data-rate communication systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz frequency synthesizer, which employs an in-phase injection-coupled QVCO (IPIC-QVCO) to produce low-phase-noise quadrature signals with low power.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
57.9 ~ 68.3 ghz 24.6mW同相注入耦合QVCO频率合成器
在60GHz频段应用等高数据速率通信系统需求不断增长的影响下,对锁相环的要求也越来越高。在毫米波直接转换收发器中,正交LO信号的产生具有挑战性。传统的正交本征信号生成方法存在许多问题。在多ghz设计中,在双LO频率的压控振荡器后加1 / 2分频器是常用的方法,但在毫米波频率下很难实现。采用无源RC复合滤波器是产生正交信号的另一种方法,但需要高功率来补偿其损耗。传统的并行耦合QVCO似乎是毫米波应用的一个很好的选择。然而,该方法存在相位噪声差的问题。本文提出了一种完全集成的57.9 ~ 68.3 ghz频率合成器,该合成器采用同相注入耦合QVCO (IPIC-QVCO)产生低功耗的低相位噪声正交信号。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A CMOS dual-switching power-supply modulator with 8% efficiency improvement for 20MHz LTE Envelope Tracking RF power amplifiers A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS A fully intraocular 0.0169mm2/pixel 512-channel self-calibrating epiretinal prosthesis in 65nm CMOS
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1