Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging

Abstract

Fan-Out wafer-level packaging (FOWLP) semi-additive process (SAP) flow for three layers of redistribution layer (RDL) has been developed. Patched dicing lane design is adopted to improve RDL plating uniformity by ~40x, as measured by sheet resistance (Rs). We demonstrate warpage correction solution to improve pattern integrity despite tool handling limitations. We also demonstrate a CMP solution to improve 2/2um L/S RDL pattern integrity by >10x. We achieve RDL mechanical integrity through an integrated endpoint-detection-controlled wet etch solution to achieve <50nm undercut and extend SAP process to sub-2/2um L/S RDL. We also establish RDL electrical integrity by integrating wafer treatment solution after RDL formation to achieve line-to-line leakage current <0.1nA. Upon completion of wafer-level process, package assembly is carried out using SAC305 BGA onto PCB. Package integrity is examined using X-ray, followed by a progressive thermal cycling (TC) reliability test. RDL mechanical and electrical integrity is proven from the board-level reliability test where the RDL layers pass 1000 TC and failure occurs on the BGA level.