Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications

Abstract

A vertical device architecture having -40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with Lg=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for VDD<;0.6V, while MOSFET is superior for VDD>;0.6V. To further improve MOSFET performance, ION needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (Cov and Cg,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.