Susceptible workload driven selective fault tolerance using a probabilistic fault model

Mauricio D. Gutierrez, V. Tenentes, T. Kazmierski
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引用次数: 5

Abstract

In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them.
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基于概率故障模型的易受影响工作负载驱动的选择性容错
本文提出了一种适用于寄存器传输级的基于概率故障模型保护逻辑电路功能的容错设计方法。该技术选择组合电路中最易受影响的工作负载,以防止概率故障的发生。工作负载敏感性是指在执行该工作负载时,任何故障绕过电路的固有逻辑屏蔽并将错误响应传播到其输出的可能性。工作负载保护是通过三模冗余(Triple Modular Redundancy, TMR)方案实现的,该方案使用了被评估为最易受影响的模式。我们将所提出的技术应用于LGSynth91和ISCAS85基准测试,并评估了其对永久错误和软错误引起的错误的容错能力。我们表明,当该技术仅用于保护32个最易受影响的模式时,与保护相同数量的易受影响模式而不对其进行排名的简化TMR方案相比,在所有检查的基准测试中,针对单个卡滞故障(永久故障)和软错误(瞬态故障)引起的错误,该技术的平均错误覆盖率分别提高了98%和94%。
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