Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection

Abstract

With growing concern about process variation in deeply nano-scaled technologies, parameterized device and circuit modeling is becoming very important for design and verification. However, the high dimensionality of parameter space is a serious modeling challenge for emerging VLSI technologies, where the models are increasingly more complex. In this paper, we propose and validate a feature selection method to reduce the circuit modeling complexity associated with high parameter dimensionality. Despite the commonly used methods such as Principal Component Analysis (PCA) and Independent Component Analysis (ICA), this method is capable of dealing with mixed Gaussian and non-Gaussian parameters, and performs a parameter selection in the input space rather than creating a new space. By considering non-linear dependencies among input parameters and outputs, the method results in an effective parameter selection. The application of this method is demonstrated in digital circuit timing analysis to effectively reduce the number of simulations. The experimental results on Double-Gate Silicon NanoWire FET (DG-SiNWFET) technology indicate 2.5x speed up in timing variation analysis of the I5CA589-s27 benchmark with a controlled average error bound of 9.4%.