A universal GNSS (GPS/Galileo/Glonass/Beidou) SoC with a 0.25mm2 radio in 40nm CMOS

Abstract

Global Navigation Satellite Systems (GNSS) have a spectrum allocation shown in Fig. 19.4.1. The time-to-first-lock and location accuracy can be improved through simultaneous reception of two different satellite signals. This usually necessitates the use of two dedicated receivers [1] driven by a single and sometimes two separate synthesizers, which increases complexity, die area, and most importantly current consumption. To solve this problem, the architecture shown in Fig. 19.4.1 is proposed. The SoC consists of one single reconfigurable low-IF receiver, a single fractional-N frequency synthesizer, and a digital baseband processor. Since different satellite signals are uncorrelated and are buried well below the noise floor, they can be amplified and downconverted by the same RF/analog chain as an image of one another, and then separated in the digital domain by the corresponding correlator and signal processor. In the case of simultaneous GPS/Galileo and Glonass dual reception, the LO (fLO_GG) is set to 1588.608MHz. As a result, the GPS/Galileo signal becomes the image of the Glonass satellite signal with an IF frequency of 13.1MHz. Similarly, when the LO (fLO_GB) is set to 1568.256MHz, the resulting IF frequency is about 7.1MHz for GPS/Galileo and Beidou dual reception. For GPS/Galileo-only reception, the LO (fLO_GPS) is set to 1571.328MHz resulting in an IF frequency of 4.092MHz.