Design of Memory System for Recursive Neural Network Hardware Accelerator

Abstract

With the remarkable effectiveness of recurrent neural network (RNN) in speech recognition, machine translation and other fields, more and more scholars at home and abroad have begun to pay attention to the research of cyclic neural network acceleration. In recent years, due to the increase of the scale of the recurrent neural network, the software can speed up the network through the weight pruning network model compression technology. The acceleration of the cyclic neural network does not only stay in the aspect of software acceleration, but also in the aspect of hardware, the acceleration strategy includes the design of RNN accelerator based on GPU, FPGA and special ASIC circuit. The storage system almost determines the upper limit of the working efficiency of the accelerator. When the input data cannot be provided to the computing unit in time, the computing unit has to enter the idle state frequently, resulting in low working efficiency. Therefore, storage systems with continuous data feeds are very important for accelerators. This paper proposes a mapping mechanism of MVM operations on hardware operation units, and proposes a storage system with continuous data feeds.