Wei-Hsiang Huang, Su-Hao Wu, Zhi-Xin Chen, Yun-Shiang Shu
{"title":"An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range","authors":"Wei-Hsiang Huang, Su-Hao Wu, Zhi-Xin Chen, Yun-Shiang Shu","doi":"10.23919/VLSIC.2019.8777944","DOIUrl":null,"url":null,"abstract":"This work presents a time-multiplexing SAR ADC to support up to 5-lead ECG monitoring with >100dB SNDR per readout channel. Its noise and linearity performance are enhanced by a combination of dual-reference architecture and mismatch error shaping (MES) technique without using amplifiers or calibration, resulting in >106dB SFDR and 109.4dB DR within 250Hz bandwidth (FoMS,DR=178.9dB). The ECG analog front-end (AFE), including 3 DC-coupled instrumentation amplifiers (IAs) and 1 ADC, occupies only 0.48mm2 in 55nm CMOS. Each ECG channel achieves 1μVrms (0.5-250Hz) input-referred noise at a low IA gain of 6V/V with a 667mVpp-diff linear input range.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"63 1","pages":"C70-C71"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8777944","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This work presents a time-multiplexing SAR ADC to support up to 5-lead ECG monitoring with >100dB SNDR per readout channel. Its noise and linearity performance are enhanced by a combination of dual-reference architecture and mismatch error shaping (MES) technique without using amplifiers or calibration, resulting in >106dB SFDR and 109.4dB DR within 250Hz bandwidth (FoMS,DR=178.9dB). The ECG analog front-end (AFE), including 3 DC-coupled instrumentation amplifiers (IAs) and 1 ADC, occupies only 0.48mm2 in 55nm CMOS. Each ECG channel achieves 1μVrms (0.5-250Hz) input-referred noise at a low IA gain of 6V/V with a 667mVpp-diff linear input range.