Reliability and parametric study on chip scale package under board-level drop test

Abstract

The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw consequently. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of displacement, and the vibration frequency is lower than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude. Several parametric studies including discussions on the chip thickness, chip size, dielectric layer thickness and hardness, and the solder ball distribution were performed to improve reliability.