Pub Date : 2009-12-01DOI: 10.1109/IMPACT.2009.5382288
Yung-Yue Chen, Shyang-Jye Chang, Yung-Hsiang Chen
There are, in practice, so many control systems possesses this kind of special feature, e.g., ballistic missile's maneuver couples with wind gusts, acceleration signal measured by accelerometers couples with the external and internal noises, and so on. Generally, the input signal u(k) is always assumed as an exactly known variable and never corrupted with noise; hence one is capable of dealing with these kinds of estimation problems by the well-known Kalman Filter that is widely used in the state estimation. Of course, it is no doubt that in the presence of unknown noise coupling input saturations, performance of Kalman Filter will be seriously degraded since the unknown input saturations coupling with input noises appear on a system model as extensive noises, and the constant processing noise variance will be not capable of covering it because of the time-variant character of these type signals.
{"title":"Estimation design of MEMS-based inertial navigation systems with noise coupling input saturation: Robust approach","authors":"Yung-Yue Chen, Shyang-Jye Chang, Yung-Hsiang Chen","doi":"10.1109/IMPACT.2009.5382288","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382288","url":null,"abstract":"There are, in practice, so many control systems possesses this kind of special feature, e.g., ballistic missile's maneuver couples with wind gusts, acceleration signal measured by accelerometers couples with the external and internal noises, and so on. Generally, the input signal u(k) is always assumed as an exactly known variable and never corrupted with noise; hence one is capable of dealing with these kinds of estimation problems by the well-known Kalman Filter that is widely used in the state estimation. Of course, it is no doubt that in the presence of unknown noise coupling input saturations, performance of Kalman Filter will be seriously degraded since the unknown input saturations coupling with input noises appear on a system model as extensive noises, and the constant processing noise variance will be not capable of covering it because of the time-variant character of these type signals.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"27 1","pages":"718-721"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82002531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/IMPACT.2009.5382232
H. Chang, W. Pan, M. Shih, Y. Lai
The purpose of this paper is to analyze the bump height variation and probe mark profile with various bump materials for wafer probing. It is necessary to establish different material bump wafer probing criteria, because the bump height variation and probe mark area have severe influence on the sort flip chip wafers that will affects the quality of the contact behavior and further impacts the flip chip assembly process reliability after wafer level probing. Standard bump wafer probing parameters can not only satisfy customer's various characters of devices, but is easy to control the appropriate bump height and probe mark quality to ensure assembly process reliability and to avoid the cold joint issue. In this paper, probing bump height and probe mark configuration with different bump materials were performed and the resultant probe marks from experiment were verified against the FE simulation results. A three-dimensional computational model was developed for analyze the contact phenomena of the solder bump and the probe. Finally, the standard bump wafer probing criteria were built by the experimental results and numerical methods. They can be used as the verified simulating model which is a useful performance evaluation tool to support the choice of suitable probe recipes and wafer probe parameters with more different bump dimensions and materials of wafer probing.
{"title":"Experimental investigation and finite element analysis of bump wafer probing","authors":"H. Chang, W. Pan, M. Shih, Y. Lai","doi":"10.1109/IMPACT.2009.5382232","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382232","url":null,"abstract":"The purpose of this paper is to analyze the bump height variation and probe mark profile with various bump materials for wafer probing. It is necessary to establish different material bump wafer probing criteria, because the bump height variation and probe mark area have severe influence on the sort flip chip wafers that will affects the quality of the contact behavior and further impacts the flip chip assembly process reliability after wafer level probing. Standard bump wafer probing parameters can not only satisfy customer's various characters of devices, but is easy to control the appropriate bump height and probe mark quality to ensure assembly process reliability and to avoid the cold joint issue. In this paper, probing bump height and probe mark configuration with different bump materials were performed and the resultant probe marks from experiment were verified against the FE simulation results. A three-dimensional computational model was developed for analyze the contact phenomena of the solder bump and the probe. Finally, the standard bump wafer probing criteria were built by the experimental results and numerical methods. They can be used as the verified simulating model which is a useful performance evaluation tool to support the choice of suitable probe recipes and wafer probe parameters with more different bump dimensions and materials of wafer probing.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"1 1","pages":"514-517"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85547785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382312
Chih-Chiang. Chang, Chun-Cheng Lin, C. Kao
This study investigated the intermixing of 95Pb5Sn solder bumps and 37Pb63Sn pre-solder in flip-chip solder joints. The reaction conditions included multiple reflows (up to 10) at 240 °C, whereby previously solder-coated parts are joined by heating without using additional solder. We found that the molten pre-solder had an irregular shape similar to a calyx (i.e., a cuplike structure) wrapped around a high-lead solder bump. The height to which the molten pre-solder ascended along the solid high-lead solder bump increased with the number of reflows. The molten pre-solder was able to reach the UBM/95Pb5Sn interface after three to five reflows. The molten pre-solder at the UBM/95Pb5Sn interface generated two important phenomena: (1) the molten solder dewetted (i.e., flowed away from the soldered surface) along the UBM/95Pb5Sn interface, particularly when the number of reflows was high, and (2) the molten pre-solder transported Cu atoms to the UBM/95Pb5Sn interface, which in turn caused the Ni-Sn compounds at the chip-side interface to change into (Cu0.6Ni0.4)6Sn5.
{"title":"Fundamental study of 95 high-lead solder bump on substrates pre-soldered with eutectic PbSn","authors":"Chih-Chiang. Chang, Chun-Cheng Lin, C. Kao","doi":"10.1109/IMPACT.2009.5382312","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382312","url":null,"abstract":"This study investigated the intermixing of 95Pb5Sn solder bumps and 37Pb63Sn pre-solder in flip-chip solder joints. The reaction conditions included multiple reflows (up to 10) at 240 °C, whereby previously solder-coated parts are joined by heating without using additional solder. We found that the molten pre-solder had an irregular shape similar to a calyx (i.e., a cuplike structure) wrapped around a high-lead solder bump. The height to which the molten pre-solder ascended along the solid high-lead solder bump increased with the number of reflows. The molten pre-solder was able to reach the UBM/95Pb5Sn interface after three to five reflows. The molten pre-solder at the UBM/95Pb5Sn interface generated two important phenomena: (1) the molten solder dewetted (i.e., flowed away from the soldered surface) along the UBM/95Pb5Sn interface, particularly when the number of reflows was high, and (2) the molten pre-solder transported Cu atoms to the UBM/95Pb5Sn interface, which in turn caused the Ni-Sn compounds at the chip-side interface to change into (Cu0.6Ni0.4)6Sn5.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"103 1","pages":"72-75"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76143383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382252
Chung-Yen Hsu, Sheng-Liang Kuo, Chun-Kai Liu, Y. Chao, M. Dai, Y.C. Wang, C.K. Lin, W. K. Wang, S. Li, Jericho Chen
GaAs based hetero-junction bipolar transistors (HBTs) offer high speed and good device matching characteristics that are attractive for many high-speed circuits. However, thermal behaviors with multi-fingers can significantly affect HBTs performance. In this paper, three dimensional (3-D) finite-element modeling (FEM) approaches are built up to analyze the maximum temperature region and temperature distribution of GaAs based HBTs devices. The thermal performance for two different types of unit cell including the standard cell and emitter thermal shunt cell were simulated and compared. As a result of generated heat from emitter fingers transfers to the substrate through the metal bridge, unit cell with emitter thermal shunt reduced the junction temperature significantly. The thermal effects of metal bridge thickness and various substrate thermal conductivity values are also discussed.
{"title":"Thermal simulation and design of GaAs HBTs","authors":"Chung-Yen Hsu, Sheng-Liang Kuo, Chun-Kai Liu, Y. Chao, M. Dai, Y.C. Wang, C.K. Lin, W. K. Wang, S. Li, Jericho Chen","doi":"10.1109/IMPACT.2009.5382252","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382252","url":null,"abstract":"GaAs based hetero-junction bipolar transistors (HBTs) offer high speed and good device matching characteristics that are attractive for many high-speed circuits. However, thermal behaviors with multi-fingers can significantly affect HBTs performance. In this paper, three dimensional (3-D) finite-element modeling (FEM) approaches are built up to analyze the maximum temperature region and temperature distribution of GaAs based HBTs devices. The thermal performance for two different types of unit cell including the standard cell and emitter thermal shunt cell were simulated and compared. As a result of generated heat from emitter fingers transfers to the substrate through the metal bridge, unit cell with emitter thermal shunt reduced the junction temperature significantly. The thermal effects of metal bridge thickness and various substrate thermal conductivity values are also discussed.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"15 1","pages":"585-588"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78126872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382147
D. Manessis, L. Boettcher, A. Ostmann, S. Karaszkiewicz, H. Reichl
allows a very high degree of miniaturization by stacking multiple layers of embedded thin components. This paper shows the realisation of embedded chip QFN-packages (Quad Flat No-Lead) with a size of 10mmx10mm which were manufactured at prototype level at 10„x14„ panels. The embedded chip in the package has a pad pitch of 100µm and the resultant QFN package has a total number of 84I/Os at 400µm footprint pitch. State-of-the-art developments in semi-additive processes by employment of laserdirect- imaging technology (LDI) have demonstrated very fine 18µm lines with 10µm space between them for the final package copper routing. The work in this paper provides evidence for chip embedding capability at very fine chip pad pitch of 100µm and discusses the technology limits. The present work at research prototype level frames the main activities in the EU-Hermes project towards the industrialisation of chip embedding technologies.
{"title":"Breakthroughs in chip embedding technologies leading to the emergence of further miniaturised system-in-packages","authors":"D. Manessis, L. Boettcher, A. Ostmann, S. Karaszkiewicz, H. Reichl","doi":"10.1109/IMPACT.2009.5382147","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382147","url":null,"abstract":"allows a very high degree of miniaturization by stacking multiple layers of embedded thin components. This paper shows the realisation of embedded chip QFN-packages (Quad Flat No-Lead) with a size of 10mmx10mm which were manufactured at prototype level at 10„x14„ panels. The embedded chip in the package has a pad pitch of 100µm and the resultant QFN package has a total number of 84I/Os at 400µm footprint pitch. State-of-the-art developments in semi-additive processes by employment of laserdirect- imaging technology (LDI) have demonstrated very fine 18µm lines with 10µm space between them for the final package copper routing. The work in this paper provides evidence for chip embedding capability at very fine chip pad pitch of 100µm and discusses the technology limits. The present work at research prototype level frames the main activities in the EU-Hermes project towards the industrialisation of chip embedding technologies.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"71 1","pages":"174-177"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80003233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382216
W. Fang, K. Liou, M. Leu
Large-scale synthesis of BiSbTe films with enhanced electrical property and Seebeck coefficient has been demonstrated in this work. As-grown BiSbTe films are found to have lower carrier concentration and higher electron mobility after the post annealing fulfilled. From the resultant high-resolution transmission electron microscope (HRTEM) images, the phenomenon of annealinginduced preferential Sb diffusion is corroborated to elaborate the reason why electrical properties could be improved. Moreover, the precipitation of Sb-rich phase is embedded in the thermally-treated BiSbTe films. Such the feasibility of large-scale fabrication of BiSbTe films with the elevated power factor is evidenced and this is very promising in the realization of room-temperature thermoelectric (TE) applications with high performances.
{"title":"Large-scale preparation of ternary BiSbTe films with enhanced thermoelectric properties using DC magnetron sputtering","authors":"W. Fang, K. Liou, M. Leu","doi":"10.1109/IMPACT.2009.5382216","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382216","url":null,"abstract":"Large-scale synthesis of BiSbTe films with enhanced electrical property and Seebeck coefficient has been demonstrated in this work. As-grown BiSbTe films are found to have lower carrier concentration and higher electron mobility after the post annealing fulfilled. From the resultant high-resolution transmission electron microscope (HRTEM) images, the phenomenon of annealinginduced preferential Sb diffusion is corroborated to elaborate the reason why electrical properties could be improved. Moreover, the precipitation of Sb-rich phase is embedded in the thermally-treated BiSbTe films. Such the feasibility of large-scale fabrication of BiSbTe films with the elevated power factor is evidenced and this is very promising in the realization of room-temperature thermoelectric (TE) applications with high performances.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"1 1","pages":"457-460"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78830377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382186
Ying-Tung Chen, J. Miao, Dau-Yuan Ning, Te-Feng Chu, Wei-En Chen
The vapor chamber heat pipe has the potential in the challenging areas to be employed as a heat spreader for cooling of high-performance microchips. This is due to not only the thickness of vapor chamber is in order of mm scale but also both the weight and the thermal resistance are less than the conventional copper heat spreaders. The operation principle of vapor chamber heat pipe is well understood and earlier studies show that the performance of vapor chamber strongly depends on the wick materials and structures. Conventional wick structure is made of sintered copper powers or base plate with micro-grooves, present work provide a novel wick design with various diamond-copper compositions to boost the effective thermal conductivity. There are three types of diamond-to-copper powder volume ratio as 1∶4, 1∶6 and 1∶8 considered in fabrication of the wick sheets and columns. An infra red (IR) thermal image camera is used to measure the steady and transient temperature distributions of the top evaporator surface of the vapor chamber by placing a single heat source with varied heat flux inputs. For performance comparison, the experimental measurements were also conducted on a solid copper block and an identical vapor chamber heat pipe with sintered copper powders of similar dimensions. Generally, the present wick material of diamond-copper composition can effectively prevent this shortcoming of dry out at high heat flux. Moreover, results also show that IR thermal imaging is a quick and effective technique for evaluating the thermal performance of vapor chamber heat pipe.
{"title":"Thermal Performance of a Vapor Chamber Heat Pipe with Diamond-Copper Composition Wick Structures","authors":"Ying-Tung Chen, J. Miao, Dau-Yuan Ning, Te-Feng Chu, Wei-En Chen","doi":"10.1109/IMPACT.2009.5382186","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382186","url":null,"abstract":"The vapor chamber heat pipe has the potential in the challenging areas to be employed as a heat spreader for cooling of high-performance microchips. This is due to not only the thickness of vapor chamber is in order of mm scale but also both the weight and the thermal resistance are less than the conventional copper heat spreaders. The operation principle of vapor chamber heat pipe is well understood and earlier studies show that the performance of vapor chamber strongly depends on the wick materials and structures. Conventional wick structure is made of sintered copper powers or base plate with micro-grooves, present work provide a novel wick design with various diamond-copper compositions to boost the effective thermal conductivity. There are three types of diamond-to-copper powder volume ratio as 1∶4, 1∶6 and 1∶8 considered in fabrication of the wick sheets and columns. An infra red (IR) thermal image camera is used to measure the steady and transient temperature distributions of the top evaporator surface of the vapor chamber by placing a single heat source with varied heat flux inputs. For performance comparison, the experimental measurements were also conducted on a solid copper block and an identical vapor chamber heat pipe with sintered copper powders of similar dimensions. Generally, the present wick material of diamond-copper composition can effectively prevent this shortcoming of dry out at high heat flux. Moreover, results also show that IR thermal imaging is a quick and effective technique for evaluating the thermal performance of vapor chamber heat pipe.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"7 1","pages":"340-343"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87595519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382284
Jung-Tang Huang, P. Lin, Po-Chin Lin, Kuo-Yu Lee, Hou-Jun Hsu
The miniaturization of components and systems has been progressing rapidly due to the developments in Micro-Electro-Mechanical (MEMS). The greatest advantage of micro injection molding is that it can massively produce micro-components rapidly with low-cost. Due to the poor flow capability of melting plastics into micro channel, and the additions of the engineering-plastics and fibers, it is difficult to inject the melted plastics into the cavities of the mold. In order to apply the microinjection technique in the fabrication of microfluidic chip, raising cavity surface temperature will be one of the solutions and reduce the cycle-time. High mold temperature not only improves the replication capacity of micro-structures but also effectively reduces molecular orientation. Therefore, developing systems for rapidly heating and cooling for injection of microfluidic chip is the main objective of this study. Numerical computations of eddy currents and heat conduction have been carried out by using the finite-element method (FEM). A simulation tool is also developed by integration of both thermal and electromagnetic analysis modules of ANSYS. Coil current, coil to plate distance and heating time are varied for both experiments and simulations. Several modifications, such as spacing in between coil turns, the distance of the workpiece and the coils, and dimensional parameters, are carried out. The capability and accuracy of simulations on the induction heating are verified from experiments, the simulated temperature distributions show reasonable agreement with measured results. To evaluate the feasibility and efficiency of induction heating on the mold surface temperature control. The size of mold plate heated by induction heating is 80×70×10 mm3. The mold plate can be rapidly heated from room temperature to about 120°C in 20 s. The simulation of the mold surface temperature with respect to time is consistent with measured results.
{"title":"The development of high frequency induction heating embedded coil","authors":"Jung-Tang Huang, P. Lin, Po-Chin Lin, Kuo-Yu Lee, Hou-Jun Hsu","doi":"10.1109/IMPACT.2009.5382284","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382284","url":null,"abstract":"The miniaturization of components and systems has been progressing rapidly due to the developments in Micro-Electro-Mechanical (MEMS). The greatest advantage of micro injection molding is that it can massively produce micro-components rapidly with low-cost. Due to the poor flow capability of melting plastics into micro channel, and the additions of the engineering-plastics and fibers, it is difficult to inject the melted plastics into the cavities of the mold. In order to apply the microinjection technique in the fabrication of microfluidic chip, raising cavity surface temperature will be one of the solutions and reduce the cycle-time. High mold temperature not only improves the replication capacity of micro-structures but also effectively reduces molecular orientation. Therefore, developing systems for rapidly heating and cooling for injection of microfluidic chip is the main objective of this study. Numerical computations of eddy currents and heat conduction have been carried out by using the finite-element method (FEM). A simulation tool is also developed by integration of both thermal and electromagnetic analysis modules of ANSYS. Coil current, coil to plate distance and heating time are varied for both experiments and simulations. Several modifications, such as spacing in between coil turns, the distance of the workpiece and the coils, and dimensional parameters, are carried out. The capability and accuracy of simulations on the induction heating are verified from experiments, the simulated temperature distributions show reasonable agreement with measured results. To evaluate the feasibility and efficiency of induction heating on the mold surface temperature control. The size of mold plate heated by induction heating is 80×70×10 mm3. The mold plate can be rapidly heated from room temperature to about 120°C in 20 s. The simulation of the mold surface temperature with respect to time is consistent with measured results.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"1 1","pages":"701-704"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88313584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382217
Chih-Jong Chang, Chih-Hao Chang, Jen-Dong Hwang, C. Kuo
Due to the development of high power density and high heat flux of IC and LED components and devices, the thermal management of microelectronics has become a very critical issue in 3C and optoelectronic industries. This has lead to the requirement of high thermal performance materials and thermal modules. To enhance the thermal performance of current thermal modules, it is very important to develop advanced thermal management materials to replace the conventional monolithic metals. In this study some kinds of graphites reinforced aluminum matrix composites were developed. The effects of reinforcement types and its volume fraction on thermal properties such as thermal conductivity as well as the thermal expansion coefficient were studied. Moreover, their thermal performance such as heat spreading resistance and thermal resistance compared to pure aluminum and copper were also conducted. From the results, it showed that the thermal conductivity of graphite/Al composites can reach to 500~600 W/m.K in X-Y plane and 40~100 W/m.K in cross plane with thermal expansion less than 10 ppm/K and density less than 2.5 g/cc; The spreading resistance of this composite is 2~5% lower than the one of pure copper, and 25% lower than the one of pure aluminum.
{"title":"Thermal characterization of high thermal conductive graphites reinforced aluminum matrix composites","authors":"Chih-Jong Chang, Chih-Hao Chang, Jen-Dong Hwang, C. Kuo","doi":"10.1109/IMPACT.2009.5382217","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382217","url":null,"abstract":"Due to the development of high power density and high heat flux of IC and LED components and devices, the thermal management of microelectronics has become a very critical issue in 3C and optoelectronic industries. This has lead to the requirement of high thermal performance materials and thermal modules. To enhance the thermal performance of current thermal modules, it is very important to develop advanced thermal management materials to replace the conventional monolithic metals. In this study some kinds of graphites reinforced aluminum matrix composites were developed. The effects of reinforcement types and its volume fraction on thermal properties such as thermal conductivity as well as the thermal expansion coefficient were studied. Moreover, their thermal performance such as heat spreading resistance and thermal resistance compared to pure aluminum and copper were also conducted. From the results, it showed that the thermal conductivity of graphite/Al composites can reach to 500~600 W/m.K in X-Y plane and 40~100 W/m.K in cross plane with thermal expansion less than 10 ppm/K and density less than 2.5 g/cc; The spreading resistance of this composite is 2~5% lower than the one of pure copper, and 25% lower than the one of pure aluminum.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"14 1","pages":"461-464"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90383190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382258
Kuen-da Chen, Hao Chen, Y. Yen
This study investigates the interfacial reactions between three kinds of lead-free solders, Sn-0.7 wt%Cu (SC), Sn-58 wt%Bi (SB) and Sn-9 wt%Zn (SZ), and Au/Ni/SUS 304 substrates. The reaction temperatures were at 240, 255 and 270 °C, and the reactions times were varied between 1 to 5 hours. According to experimental results, only the (Cu,Ni)6Sn5 phase was found in the SC/Au/Ni/SUS 304 couples. When the Ni layer was completely consumed, the massive spalling of the (Cu,Ni)6Sn5 phase was found in the solder. And then the FeSn2 phase was formed at the SUS 304 surface. Only the Ni3Sn4 phase was found at the SB/Au/Ni/SUS 304 interface. In the SZ/Au/Ni/SUS 304 couple, the Ni5Zn21 phase was formed at the interface. The thickness of the IMC in the SB/Au/Ni/SUS 304 and SZ/Au /Ni/SUS 304 couples increased with increasing the reaction time.
{"title":"Interfacial reactions of Sn-0.7Cu, Sn-58Bi and Sn-9Zn lead-free solders with the Au/Ni/SUS 304 substrate","authors":"Kuen-da Chen, Hao Chen, Y. Yen","doi":"10.1109/IMPACT.2009.5382258","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382258","url":null,"abstract":"This study investigates the interfacial reactions between three kinds of lead-free solders, Sn-0.7 wt%Cu (SC), Sn-58 wt%Bi (SB) and Sn-9 wt%Zn (SZ), and Au/Ni/SUS 304 substrates. The reaction temperatures were at 240, 255 and 270 °C, and the reactions times were varied between 1 to 5 hours. According to experimental results, only the (Cu,Ni)<inf>6</inf>Sn<inf>5</inf> phase was found in the SC/Au/Ni/SUS 304 couples. When the Ni layer was completely consumed, the massive spalling of the (Cu,Ni)<inf>6</inf>Sn<inf>5</inf> phase was found in the solder. And then the FeSn2 phase was formed at the SUS 304 surface. Only the Ni<inf>3</inf>Sn<inf>4</inf> phase was found at the SB/Au/Ni/SUS 304 interface. In the SZ/Au/Ni/SUS 304 couple, the Ni<inf>5</inf>Zn<inf>21</inf> phase was formed at the interface. The thickness of the IMC in the SB/Au/Ni/SUS 304 and SZ/Au /Ni/SUS 304 couples increased with increasing the reaction time.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"16 1","pages":"606-608"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88786467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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