E. San Andrés, M. Pampillón, C. Cañadilla, P. C. Feijoo, A. del Prado
{"title":"Towards high-k integration with III-V channels: Interface optimization of high pressure sputtered gadolinium oxide on indium phospide","authors":"E. San Andrés, M. Pampillón, C. Cañadilla, P. C. Feijoo, A. del Prado","doi":"10.1109/CDE.2013.6481333","DOIUrl":null,"url":null,"abstract":"We studied the electrical properties of metal-oxide-semiconductor devices based on Gd2O3 deposited on InP by high pressure sputtering and a novel plasma oxidation process. The resulting devices show fully functional capacitance curves., indicating an unpinned Fermi level. The samples were annealed in forming gas at temperatures up to 550°C. We studied the interface trap density of the devices. We found out that with increasing annealing temperature the defect content decreases but at 550°C the capacitance drops and the leakage current increases., indicating a dielectric degradation.","PeriodicalId":6614,"journal":{"name":"2013 Spanish Conference on Electron Devices","volume":"35 1","pages":"25-28"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Spanish Conference on Electron Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CDE.2013.6481333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
We studied the electrical properties of metal-oxide-semiconductor devices based on Gd2O3 deposited on InP by high pressure sputtering and a novel plasma oxidation process. The resulting devices show fully functional capacitance curves., indicating an unpinned Fermi level. The samples were annealed in forming gas at temperatures up to 550°C. We studied the interface trap density of the devices. We found out that with increasing annealing temperature the defect content decreases but at 550°C the capacitance drops and the leakage current increases., indicating a dielectric degradation.