Fully integrated circuit design Aihara's chaotic neuron model

Abstract

This paper presents design of the integrated chaotic neuron using 0.8 µm single poly CMOS technology, its dynamical behavior analysis. Proposed chaotic neuron consists of several op-amps, sample and hold circuits, a nonlinear function block for chaotic signal generation, a two-phase clock circuits and sigmoid output function block. From HSPICE simulation results of the circuit, approximated empirical equations is induced. Then the dynamical responses of the chaotic neuron such as bifurcation diagram, time series, Lyapunov exponent, and average firing rate are calculated with numerical analysis.