Bump shape control on high speed copper pillar plating process in lead-free wafer level packaging

Abstract

Copper pillars have been adopted and implemented in high volume manufacturing environment as early as 2006 as a replacement for high lead bumps. It is not only lead-free, but also offers the added advantage of higher stand-off, finer pitch capability and better electromigration resistance compared to tin-lead solder bumps. Owing to its significant superior thermal and electrical properties, higher stand-off, simpler UBM structure, and lower overall cost, it is not surprising that copper pillar bump has become and will continue to be a key interconnect technology in future semiconductor packages. As the full implementation of RoHS in 2010 approaches, various chemicals have been tested for this application by IDMs and OSATs. In order to simplify the chemical management in plant and shorten learning period, most of the efforts have been made on using RDL copper plating chemistry for Cu pillar applications.