Testing molecular devices in CMOS/nano integrated circuits

Abstract

Molecular electronics may improve the speed and density of circuits as the limitations of CMOS become more stringent. However, due to the difficulties in manufacturing molecular circuits, it may be beneficial to use a hybrid model initially, composed of both molecular and CMOS components. The molecular feature size of such devices can yield high density memory applications, which are expected to reach 1011 b/cm2. The defect rate in such systems is expected to be 10%, which still makes it an attractive technology due to overhead. The goal of this paper is to investigate techniques of detecting defects within molecular electronic structures. Essentially, the proposed techniques will lead to systems that are self-healing with minimal loss of memory improving the reliability and the utility of the manufactured memory.