F. Cacho, A. Benhassain, S. Mhira, A. Sivadasan, V. Huard, P. Cathelin, V. Knopik, A. Jain, C. Parthasarathy, L. Anghel
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引用次数: 0
Abstract
Reliability for advanced CMOS nodes is becoming very challenging. The trade-off between high performance and reliability requirement can no longer be addressed by rough extra-margin. It would results in an overdesign and strong penalty of performance and area. A fine-grain analysis of mission profile is the path toward accurate assessment of ageing. A wide review of methodologies and results are presented, they are applied to digital, analog and RF/mmW circuits. Important set of experimental results are shown and compared to simulation. This paper highlights the correlation between activity profiling or workload and degradation performance induced by ageing.
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