Fast and accurate evaluation of delay in CNFET circuits

Abstract

The carbon nanotube field-effect transistor (CNFET) is a potential candidate to replace MOSFET due to advantages offered by CNFET such as its superior electrical, thermal, and mechanical properties. When designing circuits made of CNFETs, additional features such as the CNT number, positions and pitch in the array of tubes creating a transistor channel must be considered for performance evaluation. These features create additional challenges during simulation. In this paper, we analyze the effectiveness of CNFET Logical Effort (LE) model, to be used in place of simulation, for circuits with different topologies and CNFET technology (pitch) ranging from 2nm-30nm. We show that our delay evaluation tool using expanded LE model predicts delay for analyzed circuits with a very small average error of 2.15% as compared to SPICE simulations, and runs about 30 times faster. We have also evaluated our model in the presence of tube variations created by removal of unwanted metallic tubes. Our model closely correlated with Stanford SPICE model, developed for CNFET circuits, within 3%.