Morphed Standard Cell Layouts for Pin Length Reduction

Abstract

In this article we present a concept called morphed layouts which are layouts of a standard cell with different footprints on the pins of each layout. We propose two approaches to exploiting morphed layouts for pin length reduction. The first approach is performed after placement but before routing. This approach enables design space exploration to seek best trade-off between total wire length and via count. It can obtain better results than the previous work when dealing with large circuits. The second approach is applied to a routed design, which can always achieve pin length reduction without via count increase. It can on average reduce total pin length by 12.1% and total wire length by 3.4%.