Mohammad Moradinezhad Maryan, Reza Rezaei Siahrood, Hamed Sajadinia, S. J. Azhari
{"title":"Sub-threshold MOS Translinear Principle Based-Analog Cell Suitable for Current-Mode Signal Processing","authors":"Mohammad Moradinezhad Maryan, Reza Rezaei Siahrood, Hamed Sajadinia, S. J. Azhari","doi":"10.1109/IranianCEE.2019.8786399","DOIUrl":null,"url":null,"abstract":"A new low-voltage current-mode multifunction cell for analog signal processing, is presented in this paper. The proposed cell is based on sub-threshold MOS translinear (MTL) principle and consists of six matched NMOS transistors. Square-rooting, exponential and logarithmic functions are computational current-mode circuits that are designed using the proposed cell. The designed functions are simulated by HSPICE simulator in TSMC 0.18 µm (level-49 parameters) CMOS technology. Post-layout simulation results plus Monte Carlo analysis verified the functionality and superiority of the proposed circuits. Simulation results of the current-mode square-rooting circuit with 1-V DC supply voltage show that the maximum nonlinearity as 2.8%, the −3dB bandwidth as 32.95 MHz and the maximum power consumption as 520 nW.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"19 1","pages":"60-65"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IranianCEE.2019.8786399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A new low-voltage current-mode multifunction cell for analog signal processing, is presented in this paper. The proposed cell is based on sub-threshold MOS translinear (MTL) principle and consists of six matched NMOS transistors. Square-rooting, exponential and logarithmic functions are computational current-mode circuits that are designed using the proposed cell. The designed functions are simulated by HSPICE simulator in TSMC 0.18 µm (level-49 parameters) CMOS technology. Post-layout simulation results plus Monte Carlo analysis verified the functionality and superiority of the proposed circuits. Simulation results of the current-mode square-rooting circuit with 1-V DC supply voltage show that the maximum nonlinearity as 2.8%, the −3dB bandwidth as 32.95 MHz and the maximum power consumption as 520 nW.
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