Floating-point unit design with nano-electro-mechanical (NEM) relays

Abstract

Digital circuits made with nano-electro-mechanical (NEM) relays offer energy-efficiency benefits over CMOS since they have zero leakage power and can offer circuit level performance that competes with CMOS. In this paper we show how new relay circuit design techniques combined with those we already demonstrated on smaller relay blocks enable us to optimize the design of the most complex arithmetic unit, the floating-point unit (FPU). The energy, performance, and area trade-offs of FPU designs with NEM relays are examined and compared with those of state-of-the-art CMOS designs in an equivalent scaled process. Circuits that are critical path bottlenecks for the FPU specifically, most notably the leading zero detector (LZD) and leading zero anticipator (LZA), are optimized with new relay-tailored circuit techniques. These optimizations reduce the NEM relay FPU latency from 71 mechanical delays in an optimal-CMOS-style implementation to 16 mechanical delays in a generalized custom NEM relay implementation. In a 90 nm process node, the FPU designed with NEM relays is projected to achieve 15× lower energy per operation compared to the FPU designed with CMOS.