Study of Related Yield Loss and Mechanism of NOR Flash Self-Align-Source

Abstract

This paper analyzed the special failure pattern in the wafer center region of 65nm NOR flash. By circuit and failure checking, confirmed the root cause is that the low read current from the big resistance induced by photo residues in self-align-source (SAS) area. The voltage non -uniformity and check-board yield failure were ascribed to the silicon dislocation in SAS active area induced by SAS loop implant. Additional anneal, and higher temperature of rapid thermal oxide, can improve these issue by repairing the dislocation. Decreasing resistance of SAS by dose can also improve yield loss corresponding to erasing cell. All above know-hows helped us to comprehend the new clue and orientation to optimize failure induced by erase failure, and provided the experience for continuous shrinkage of floating NOR flash cell.