Chip layout impact on stress-induced mobility degradation studied with indentation

Abstract

Chip-package interaction-caused mobility degradation in CMOS transistors is a critical degradation mechanism for microelectronic devices. An approach based on nondestructive indentation is applied to induce highly localized stress fields. Strain-sensitive ring oscillator circuits are integrated to monitor parametric deviations during mechanical loading. In this study, the indentation technique is used to investigate the impact of the chip layout and geometry of a flip chip-packaged test chip. Complementary FE simulation provides a better understanding of the relevant stress-strain fields and enables a comparison of the parametric circuit deviations within a dedicated stress tensor. The results demonstrate the capability to study the stress-strain distribution in microelectronic devices during external loading with indentation and to determine its impact on transistor degradation.