Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Abstract

The Lagrangian relaxation (LR) based gate sizer proposed in [1] has the best leakage power results published so far for the ISPD 2012 Gate Sizing Contest benchmarks. However, it requires many LR iterations and does not rely on any technique to perform cell option candidate filtering in the LR subproblem solver. Therefore, this paper presents some extensions to address these drawbacks. In order to reduce the number of LR iterations, we propose some enhancements to the original LR multiplier formula. We also use a scaling factor to properly scale timing cost and leakage power in the LR local cost. Moreover, we apply a cell option candidate filtering strategy to reduce the runtime of each LR iteration. Finally, we improve the post-processing timing recovery and power recovery. Our work achieved leakage power results very close to the original algorithm, taking 4.28x fewer LR iterations, on average, and 9.11x fewer cell swaps during LR, on average.