Test results and irradiation performances of 3-D circuits developed in the framework of ATLAS hybrid pixel upgrade

IEEE Nuclear Science Symposuim & Medical Imaging Conference Pub Date : 2010-10-01 DOI:10.1109/NSSMIC.2010.5874036

P. Pangaud, D. Arutinov, M. Barbero, P. Breugnon, B. Chantepie, J. Clémens, R. Fei, D. Fougeron, M. Garcia-Sciveres, S. Godiot, T. Hemperek, M. Karagounis, H. Kruger, A. Mekkaoui, L. Perrot, S. Rozanov, N. Wermes

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引用次数: 3

Abstract

Vertex detectors for High Energy Physics experiments require pixel detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness. A way to face new challenges of ATLAS/SLHC future hybrid pixel vertex detectors is to use the emerging 3-D Integrated Technologies. However, commercial offers of such technologies are only very few and the 3-D designer's choice is then hardly constrained. Moreover, as radiation hardness and specially SEU tolerance of configuration registers is a crucial issue for SLHC vertex detectors and, as commercial data on this point are always missing, a reliable qualification program is to be developed for any candidate technology. We will present the design and test (including radiation tests with 70 kV, 60W X-Ray source and 24 GeV protons) of Chartered, 130nm Low Power 2-D chips realized for this qualification.

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在ATLAS混合像元升级框架下开发的三维电路的测试结果和辐照性能

用于高能物理实验的顶点检测器要求像素检测器具有较高的空间分辨率、良好的信噪比和辐射硬度。面对ATLAS/SLHC未来混合像素顶点探测器的新挑战，一种方法是使用新兴的3-D集成技术。然而，这种技术的商业供应很少，3d设计师的选择几乎没有限制。此外，由于配置寄存器的辐射硬度和特殊的SEU公差是SLHC顶点检测器的关键问题，并且由于这一点上的商业数据总是缺失，因此需要为任何候选技术开发可靠的资格认证程序。我们将介绍为本次资质而实现的特许130nm低功耗二维芯片的设计和测试(包括70kv, 60W x射线源和24gev质子的辐射测试)。

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IEEE Nuclear Science Symposuim & Medical Imaging Conference

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