A 4× 25-to-28Gb/s 4.9mW/Gb/s −9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects

Abstract

Growing data traffic requires low-power 25Gb/s-class optical interconnects for board-to-board transmission inside ICT systems [1-4]. The main power consumption of an optical link strongly depends on the sensitivity of the TIA; thus, development of a high-sensitivity TIA is a key to creating a low-power optical link., There are two challenges concerning the design of such a TIA: (1) improving the sensitivity of TIA without sacrificing bandwidth and (2) suppressing ISI due to insertion loss. To address these two issues, a 4×25Gb/s CMOS optical receiver (RX), which includes a four-channel TIA and a PD array operating at 1.3μm wavelength, is developed. The key components of the TIA are an automatic-decision-threshold control (ATC) with an offset canceller and low-voltage output driver (Drv) with peaking value of 7.7dB at 12.5GHz, achieved by separating equalizer (EQ) function and output buffer (BUF). The TIA attains a sensitivity of -9.7dBm (86μApp) optical modulation amplitude (OMA) and an eye opening of 65% at 25Gb/s. Operation at 28Gb/s with sensitivity of -8.2dBm (121μApp) OMA is also confirmed.