Y-junction based addressing in optical symmetric multiprocessor networks

Abstract

We have focused on the main scaling issues associated with symmetric multiprocessor architectures. As a solution, we have devised an optical binary tree architecture based on optical time division multiplexing consisting of dual Y-junction splitter/combiner for backplane and on-board interconnections. We have shown the design of 1x8 splitter with loss of 8.325dB for backplane and lx4 splitters with losses of 6.53dB for onboard interconnection. This optical SMP network provides distinct performance and cost advantages over traditional electronic interconnect and even over other optical interconnection networks.