Deep State Encryption for Sequential Logic Circuits

Abstract

Logic encryption has been proposed as a potential solution to the hardware IP piracy problem. Naive logic encryption methods were shown to be susceptible to Boolean satisfiability (SAT) based attacks. In addition, the recently proposed Sequential SAT attack is able to decrypt many encrypted sequential logic circuits. This paper introduces a new logic encryption scheme that encrypts a sequential circuit on the occurrence of a chosen deep state. Two novel techniques to select a suitable deep state from the gate-level netlist of the design have been introduced. The attack resiliency of the proposed encryption technique against the sequential SAT attack is demonstrated using several standard benchmark circuits.