Effect of CD logic on multiplier accumulator unit

Abstract

A high performance, Low power and high speed designs are always being important in VLSI. There are different logic families exist for an efficient performance of the circuits. The Constant Delay (CD) logic style is one of the efficient logics among the digital logic family. The complicated logic expressions in the digital logic families are implemented using this high performance energy efficient logic style (Constant delay). Multiplier Accumulator Unit is the most important component in applications such as Digital Signal Processing, Field Effect Transistors, and Finite impulse response filters. A high speed and energy efficient Multiplier Accumulator unit using constant delay logic is implemented in this paper, and the performance parameters such as power, delay and power delay product (PDP) are measured. The simulation is done using HSPICE tool in both 45nm CMOS technology and 32nm CMOS technology.