{"title":"A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology","authors":"Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, G. Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung-Yen Liao","doi":"10.1109/VLSIC.2012.6243765","DOIUrl":null,"url":null,"abstract":"A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm2. This chip drains 24mW from a 1.2V power supply.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243765","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm2. This chip drains 24mW from a 1.2V power supply.
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