Output Improvement in High Volume Memory Fabs by Reducing Recipe Qualifications

C. Keith, Ace Chen, Haim Albalak, Maryam Anvar
{"title":"Output Improvement in High Volume Memory Fabs by Reducing Recipe Qualifications","authors":"C. Keith, Ace Chen, Haim Albalak, Maryam Anvar","doi":"10.1109/ASMC49169.2020.9185365","DOIUrl":null,"url":null,"abstract":"This paper presents a model to optimize the number of recipes qualified on each tool or chamber in a fleet by evaluating the trade-off between the cost in tool time required to run nonproduct wafers (NPW’s) for qualifying additional recipes versus the benefit of having as many recipes as possible qualified to maximize flexibility. The model specifically addresses an issue observed in high volume fabs such as large memory fabs, where most of the tools are qualified to run several recipes. In these situations, in which the number of tools is much greater than the number of recipes and substantial resources (such as process and metrology tool time, non-product wafers, and labor) are required to qualify each recipe, the cost in tool time for qualifying many recipes on each tool can outweigh the benefits in flexibility. Based on typical product mixes and qualification requirements in such a fab, we demonstrate that using this model could reduce the tool time required to run qualification wafers and increase the time available to run production wafers by 1% or more with minimal or no impact on cycle time.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"60 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC49169.2020.9185365","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

This paper presents a model to optimize the number of recipes qualified on each tool or chamber in a fleet by evaluating the trade-off between the cost in tool time required to run nonproduct wafers (NPW’s) for qualifying additional recipes versus the benefit of having as many recipes as possible qualified to maximize flexibility. The model specifically addresses an issue observed in high volume fabs such as large memory fabs, where most of the tools are qualified to run several recipes. In these situations, in which the number of tools is much greater than the number of recipes and substantial resources (such as process and metrology tool time, non-product wafers, and labor) are required to qualify each recipe, the cost in tool time for qualifying many recipes on each tool can outweigh the benefits in flexibility. Based on typical product mixes and qualification requirements in such a fab, we demonstrate that using this model could reduce the tool time required to run qualification wafers and increase the time available to run production wafers by 1% or more with minimal or no impact on cycle time.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
通过减少配方资格来提高大容量内存晶圆厂的产量
本文提出了一个模型,通过评估运行非产品晶圆(NPW)所需的工具时间成本与拥有尽可能多的合格配方以最大限度地提高灵活性之间的权衡,来优化车队中每个工具或腔室的合格配方数量。该模型专门解决了在大容量晶圆厂(如大内存晶圆厂)中观察到的问题,其中大多数工具都有资格运行多个配方。在这些情况下,工具的数量远远大于配方的数量,并且需要大量的资源(例如过程和计量工具时间、非产品晶圆和劳动力)来鉴定每个配方,在每个工具上鉴定许多配方的工具时间成本可能超过灵活性的好处。基于这种晶圆厂的典型产品组合和认证要求,我们证明使用该模型可以减少运行认证晶圆所需的工具时间,并将可用的生产晶圆运行时间增加1%或更多,而对周期时间的影响最小或没有影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Systematic Missing Pattern Defects Introduced by Topcoat Change at PC Lithography: A Case Study in the Tandem Usage of Inspection Methods Computational Process Control Compatible Dimensional Metrology Tool: Through-focus Scanning Optical Microscopy Characterization of Sub-micron Metal Line Arrays Using Picosecond Ultrasonics An Artificial Neural Network Based Algorithm For Real Time Dispatching Decisions A Framework for Semi-Automated Fault Detection Configuration with Automated Feature Extraction and Limits Setting
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1