Low Power SOC Based on High Density MIM Capacitor for beyond Moore Era by Robust Power Integrity Achievement

Abstract

In this paper, the methods for improving the PI (Power Integrity) of low power SOC (System-On-Chip) are discussed. In order to confirm the PI improvement effect by using MIM (Metal-Insulator-Metal), system-level PDN impedance and voltage drop was analyzed for cores with one LICC (Low Inductance Ceramic Capacitor) embedded in the package. Compared to the case where no decoupling capacitor was applied, the PI characteristics were improved when the LICC (Low Inductance Ceramic Capacitor) was inserted in the package substrate, and more dramatic improvement can be achieved by using MIM. When the embedded decoupling capacitor and the MIM capacitor corresponding to the core area are used at the same time, the system-level PDN impedance is reduced by less than half compared with the case where only the embedded LICC is used. Also, it was confirmed by simulation and measurement that voltage drop and voltage ripple can be reduced by implementing MIM. In particular, MIM has been analyzed to be more effective at high frequencies than conventional ceramic capacitors, making it a suitable PI improvement solution for the beyond Moore era.