Fine Line and Low Stress RDL Solition for Fan-Out Wafer Level & Panel Level Packaging

Abstract

Process limitations faced during the construction and integration of current and next generation advanced packages require a new RDL (Redistribution Layer) approach to overcome fine L/S and stress constraints. If interactions between design, process and materials are not optimized or controlled, then yield loss and higher cost result. RDL is an integral part of a package and with greater design complexity the number of such layers also increase. This paper introduces a new RDL concept through HRDP® (High Resolution Debondable Panel) technology. It has received industry wide attention, especially for Fan-Out, Chip Last, Wafer Level & Panel Level package assemblies. The structure and materials for HRDP® are described. The applicable HRDP® carrier can be provided in various dimensions and thicknesses for round panels and for square/rectangular panels with glass or silicon to match customer requirements. This accommodates process simplification and improves interfacial stresses. The process steps using HRDP® are elaborated, which essentially use existing tools in RDL metal patterning (i.e., Lithography, Developer/Descum etc.) without disrupting the assembly line layout and process flow. HRDP® is compatible with existing dielectrics and photoresists. It has been demonstrated that based upon the capabilities of dielectrics and photoresists used for RDL in the bump fab, fine L/S geometries of 2/2 um and less have been achieved. Reliability data has been shared.