New Trench gate LDMOS for low power applications

Abstract

A trench gate SOI LDMOS with an oxide trench in the drift region and a trench source plate (TG-LDMOS) is proposed to obtain a high breakdown voltage (BV) and low specific on-resistance (R_sp) simultaneously. The oxide trench extends the drift region in the vertical direction and reshapes the electric field, resulting in reduced cell pitch and R_sp. The trench source plate extends to the buried oxide layer (BOX) further enhances the RESURF effect and also works as a dielectric isolation trench. BV of 111V and R_sp of 0.87mΩ·cm² are obtained for the TG-LDMOS with 3μm cell pitch. Compared with conventional LDMOS (C-LDMOS), R_sp of the TG-LDMOS decreases by 63.8%, the transconductance(g_m) increases by 8.3% and the switching delay decreases by 32% at the same BV. Furthermore, the figure-of-merit (FOM=BV²/R_sp) of the TG-LDMOS equals to 14.6MW/cm², exhibiting 172.7% improvement than that of C-LDMOS.