A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS

Abstract

An energy-efficient AES hardware accelerator based on 2-Sbox 8-bit datapath is fabricated in 28nm CMOS for IoT and mobile SoC applications. It obtains the smallest encryption cycles of 113 of 8b-AES by 100% utilization of two Sboxes and rearranging data bytes processing order. It also minimizes intermediate data registers (InterReg) to only 40b from 256b by eliminating ShiftRow and MixColumn registers. Along with glitch reduction design of Sbox in native GF $( 2 ^{4})^{2}$ composite-field, it achieves best-in-class efficiency of 257-923 Gbps/W and 28–991Mbps throughput rate at 0.41/0.9V with scalable voltage down to near-threshold.