A comprehensive model for crossbar memory arrays

Abstract

A crossbar array model with complete solutions for arbitrary memory and selector device behaviors (e.g., nonlinear, rectifying, etc.) is presented in this paper to analyze various array designs and device options. Voltage/current decay due to line resistance limits practical size of linear crossbar arrays below 10kbit. Less than 2% current reaches the end of a line in a small 1kbit array. Nonlinearity in memory characteristics and select diodes improve sensing margin from below 5% to above 30% in a 1kbit array. The voltage window between selected and unselected devices is increased from <;5%Vdd to >;20%Vdd by nonlinearity and >;40%Vdd by select diodes. This model provides quantitative evaluation for crossbar array designs and enables statistical analysis of array characteristics.