{"title":"Alternative FCBGA Package Solution Evaluation: High-speed Design Optimization and Electrical Characterization of FOBGA","authors":"Hung-Hsiang Cheng, Cheng-Yu Wu, H. Kuo, Chen-Chao Wang, Guo-Cheng Liao, Yun-Hsiang Tien, Yi-Chuan Ding","doi":"10.4071/1085-8024-2021.1.000119","DOIUrl":null,"url":null,"abstract":"\n There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV SoCs. The other package solution is Fan-out Ball Grid Array (FOBGA) which is targeting larger FCBGA with high ABF layer count. The focused maximum package size and layer count of FCBGA are 55 mm x 55 mm and 6+2+6L individually. The potential applications are CPUs, AI accelerators, and networking switches which require extremely high electrical performance. The design concept of FOBGA is to redistribute signal bump locations on FO die, and make an ABF substrate layer accommodate more I/O signals to further reduce the layer count of the ABF substrate. The package signal integrity (SI) and power integrity (PI) analyses are performed to validate the electrical performance of proposed package solutions. Finally, we come out with design guidelines of FOBGA to mitigate the performance degradation due to substrate layer reduction.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"143 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4071/1085-8024-2021.1.000119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV SoCs. The other package solution is Fan-out Ball Grid Array (FOBGA) which is targeting larger FCBGA with high ABF layer count. The focused maximum package size and layer count of FCBGA are 55 mm x 55 mm and 6+2+6L individually. The potential applications are CPUs, AI accelerators, and networking switches which require extremely high electrical performance. The design concept of FOBGA is to redistribute signal bump locations on FO die, and make an ABF substrate layer accommodate more I/O signals to further reduce the layer count of the ABF substrate. The package signal integrity (SI) and power integrity (PI) analyses are performed to validate the electrical performance of proposed package solutions. Finally, we come out with design guidelines of FOBGA to mitigate the performance degradation due to substrate layer reduction.