Alternative FCBGA Package Solution Evaluation: High-speed Design Optimization and Electrical Characterization of FOBGA

Hung-Hsiang Cheng, Cheng-Yu Wu, H. Kuo, Chen-Chao Wang, Guo-Cheng Liao, Yun-Hsiang Tien, Yi-Chuan Ding
{"title":"Alternative FCBGA Package Solution Evaluation: High-speed Design Optimization and Electrical Characterization of FOBGA","authors":"Hung-Hsiang Cheng, Cheng-Yu Wu, H. Kuo, Chen-Chao Wang, Guo-Cheng Liao, Yun-Hsiang Tien, Yi-Chuan Ding","doi":"10.4071/1085-8024-2021.1.000119","DOIUrl":null,"url":null,"abstract":"\n There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV SoCs. The other package solution is Fan-out Ball Grid Array (FOBGA) which is targeting larger FCBGA with high ABF layer count. The focused maximum package size and layer count of FCBGA are 55 mm x 55 mm and 6+2+6L individually. The potential applications are CPUs, AI accelerators, and networking switches which require extremely high electrical performance. The design concept of FOBGA is to redistribute signal bump locations on FO die, and make an ABF substrate layer accommodate more I/O signals to further reduce the layer count of the ABF substrate. The package signal integrity (SI) and power integrity (PI) analyses are performed to validate the electrical performance of proposed package solutions. Finally, we come out with design guidelines of FOBGA to mitigate the performance degradation due to substrate layer reduction.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"143 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4071/1085-8024-2021.1.000119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV SoCs. The other package solution is Fan-out Ball Grid Array (FOBGA) which is targeting larger FCBGA with high ABF layer count. The focused maximum package size and layer count of FCBGA are 55 mm x 55 mm and 6+2+6L individually. The potential applications are CPUs, AI accelerators, and networking switches which require extremely high electrical performance. The design concept of FOBGA is to redistribute signal bump locations on FO die, and make an ABF substrate layer accommodate more I/O signals to further reduce the layer count of the ABF substrate. The package signal integrity (SI) and power integrity (PI) analyses are performed to validate the electrical performance of proposed package solutions. Finally, we come out with design guidelines of FOBGA to mitigate the performance degradation due to substrate layer reduction.
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替代FCBGA封装方案评估:FOBGA的高速设计优化和电学特性
有两种潜在的替代封装方案提出了用味之素积聚膜(ABF)衬底取代倒装芯片球栅阵列(FCBGA)。第一种是不含abf的解决方案,即采用层状预浸料的倒装芯片规模封装(FCCSP)。FCCSP是一种成熟的封装解决方案,可以选择多种预浸料来匹配原始ABF表征。FCCSP的聚焦FCBGA尺寸从10mm × 10mm到21mm × 21mm,衬底层数从1+2+1L到2+2+2L。这些应用包括内存控制器、Wi-Fi处理器和数字电视soc。另一种封装解决方案是扇出球栅阵列(FOBGA),其目标是具有高ABF层数的更大的FCBGA。FCBGA的最大封装尺寸和层数分别为55 mm × 55 mm和6+2+6L。潜在的应用是cpu、人工智能加速器和网络交换机,这些都需要极高的电气性能。FOBGA的设计理念是在FO芯片上重新分配信号碰撞位置,使ABF基板层容纳更多的I/O信号,进一步减少ABF基板的层数。进行了封装信号完整性(SI)和功率完整性(PI)分析,以验证所提出的封装解决方案的电气性能。最后,我们提出了FOBGA的设计准则,以减轻由于衬底层减少而导致的性能下降。
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