Fan-out ultrasound transducer array in substrate

Abstract

The idea that employs an advanced package that combines Embedded Substrate Level Package with Fan-out Substrate Level Package is proposed to package high-density and high-frequency ultrasound transducer array. We successfully verified the process principle. The material of the sample array is lead zirconated titanite piezoelectric ceramic and silicon dummy chip, which total size of arrays is 5000μm× 5000μm×140μm. Arrays are divided into 50×50 elements. Each element size was 70μm × 70 μm×140μm. The kerf between two adjacent array elements is 30μm. We successfully fan out the signal trace of two 1×44 linear arrays in the 50×50 area array using a single-layer re-distribution layer. The impedance curve was measured on the impedance meter. The blind via diameter on the linear array is 30μm, and the line/spacing is 50μm/50μm. We try to fan out a 4×16 planar array in the 50×50 planar array using a single-layer re-distribution layer. The blind via diameter on the planar array is 20μm, and the line width and spacing are 20μm/15μm. However, some questions are leading to the low yield of this process. We analyze the reasons for the low yield.