Yi-Ming Chen, Shih-Cheng Lin, Sheng-Fuh Chang, Hsin-Yen Yang
{"title":"A compact CMOS single-ended-to-balanced bandpass filter in millimeter-wave band","authors":"Yi-Ming Chen, Shih-Cheng Lin, Sheng-Fuh Chang, Hsin-Yen Yang","doi":"10.1109/MWSYM.2017.8058893","DOIUrl":null,"url":null,"abstract":"This paper presents a compact 55–65 GHz single-ended-to-balanced bandpass filter in CMOS technology. The bandpass filters is designed based on three-line stepped-impedance resonator to obtain differential output phases. The stepped-impedance open stub is incorporated to generate stopband transmission zero. To meet the stringent chip area restriction in CMOS realization, the grounded pedestal structure is adopted by fully utilizing the multiple metal layer feature. The measured insertion loss is less than 4.7 dB and the return loss is larger than 9 dB in 55–65 GHz. The power imbalance is less than 0.7 dB and the phase imbalance is less than 2°. The chip size without pad is 0.293×0.136 mm2, equivalent to 0.007 Ig2.","PeriodicalId":6481,"journal":{"name":"2017 IEEE MTT-S International Microwave Symposium (IMS)","volume":"16 1","pages":"1453-1455"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE MTT-S International Microwave Symposium (IMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2017.8058893","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a compact 55–65 GHz single-ended-to-balanced bandpass filter in CMOS technology. The bandpass filters is designed based on three-line stepped-impedance resonator to obtain differential output phases. The stepped-impedance open stub is incorporated to generate stopband transmission zero. To meet the stringent chip area restriction in CMOS realization, the grounded pedestal structure is adopted by fully utilizing the multiple metal layer feature. The measured insertion loss is less than 4.7 dB and the return loss is larger than 9 dB in 55–65 GHz. The power imbalance is less than 0.7 dB and the phase imbalance is less than 2°. The chip size without pad is 0.293×0.136 mm2, equivalent to 0.007 Ig2.