Practical considerations for high throughput wafer level tests of silicon-photonics integrated devices

Abstract

Optical communication has recently seen a resurgence driven by the demand for high-speed networking. Silicon Photonics (SiPh) has gained recent interest as a low cost and high volume method for creating photonic integrated circuits (PIC). PICs create new challenges for manufacturability since the devices require optical probing in addition to RF probing. This paper discusses a low cost method for aligning an optical fiber to a vertical grating coupler for wafer optical probing using a pre-defined device layout. This method is suitable for high volume wafer manufacturing. The alignment takes 0.5-1.5s and is reliable across multiple products and designs.