A quad-core 28–32 GHz transmit/receive 5G phased-array IC with flip-chip packaging in SiGe BiCMOS

K. Kibaroglu, M. Sayginer, Gabriel M. Rebeiz
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引用次数: 38

Abstract

This work presents a quad-core 28–32 GHz transmit/receive phased-array integrated circuit (IC) with flipchip packaging for 5G communication links. The IC consists of 4 Tx/Rx channels each with 6-bit phase and 14 dB amplitude control. The noise figure in the RX mode is 4.6 dB, the lowest reported to date to our best knowledge, and the output power in transmit mode is 10 dBm at P1dB. The power consumption is 105 mW and 200 mW in the RX and TX modes respectively, per channel. The chip is flipped on a low cost RF board with a 2×2 antenna array for a range of system-level measurements. The array has a measured EIRP of 24.5 dBm, and is used in a 1 meter communication link achieving 64-QAM 2.4 Gbps data rate with an EVM of 2.89%.
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采用SiGe BiCMOS倒装封装的四核28 - 32ghz发射/接收5G相控阵集成电路
这项工作提出了一种用于5G通信链路的四核28-32 GHz发射/接收相控阵集成电路(IC),采用倒装封装。该IC由4个Tx/Rx通道组成,每个通道具有6位相位和14 dB幅度控制。RX模式下的噪声系数为4.6 dB,是迄今为止我们所知的最低报告,而发射模式下的输出功率为P1dB时的10 dBm。在RX和TX模式下,每通道的功耗分别为105兆瓦和200兆瓦。该芯片被翻转在一个低成本的射频板上,带有2×2天线阵列,用于一系列系统级测量。该阵列的测量EIRP为24.5 dBm,用于1米通信链路,实现64-QAM 2.4 Gbps数据速率,EVM为2.89%。
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