What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator?

Abstract

A novice continuous-time delta-sigma designer is faced with an admittedly complex maze of possible design choices. The right architecture often determines how efficiently the modulator can be implemented. This paper critically examines various popular delta-sigma architectures. It concludes that a single-bit modulator with FIR feedback is a prime candidate that enables a power-efficient implementation for a variety of specifications. To support this thesis, measurement results of an audio delta-sigma modulator, designed in a 65 nm CMOS process are given. The modulator, which incorporates FIR feedback and chopping to reduce 1/f noise, achieves 98.6 dB peak SNDR in a 24 kHz bandwidth and consumes only 260 μ W from a 1.2 V supply.