Abnormal transconductance enhancement effects induced by negative bias-stress at high temperature in amorphous-InGaZnO thin-film transistors

Abstract

This letter investigates the effect of negative bias stress induced abnormal degradation in amorphous InGaZnO thin-film transistors (TFTs) at high temperature. Drain current-gate voltage (ID-VG) and capacitance-voltage (C-V) measurements are employed to analyze degradation mechanism. High temperature negative bias stress lead to not only a negative parallel shift in ID-VG but also a C-V distortion at off-state. This attributes to a barrier lowering effect nearby both drain and source sides according to symmetrical hole-trapping effect. Furthermore, both on-current and subthreshold swing will be improved due to the localized hole-trapping near source and drain.