A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

Abstract

Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.