A Realizable Digital Bubble Sorting SAR ADC Calibration Technology

Abstract

This paper proposes a SAR ADC front-end calibration technique based on sorting and recombination of capacitor arrays to mitigate the impact of capacitor mismatch on the performance of high-precision SAR ADCs. This method performs proper and effective sorting and reconstruction of the unit capacitors in the capacitor array before the SAR ADC performs data conversion. In addition, an achievable digital bubble sorting module is proposed to be used in this sorting scheme, which overcomes the limitation that the analog bubble sorting module cannot be applied to high-precision SAR ADC due to the complexity of the analog bubble sorting module. For the C-DAC using N unit capacitors, a digital bubble sorting circuit is used instead of an analog bubble sorting circuit, which can reduce the number of digital-to-analog connection signal lines from N2 to N. A 1 MS/s 8-bit SAR ADC is designed based on XFAB 0.18 μm process to verify this method. The results show that before and after calibration, SNDR is increased by 3.6 dB, SFDR is increased by 11.9 dB, and ENOB can reach 7.9. The method is simple and reliable, and is suitable for various SAR ADCs based on charge redistribution structures.