Interlayer Engineering in GeSn Gate Stacks for Advanced CMOS

Abstract

This work reports a comparative study of different interlayers (ILs) in low thermal budget gate stacks on GeSn substrates with 8.5% and 11% of Sn concentration. It is shown through electrical capacitance-voltage $(C-V)$ and xray photoelectron spectroscopy (XPS) characterization that aluminum-based ILs help in reducing the density of interface traps $(\mathrm{D}_{it})$ by suppressing Sn-O formation during HfO2 high k dielectric deposition. Pre-oxidation before IL deposition was found to be essential to reduce the C–V stretch-out indicating reduction in $\mathrm{D}_{it}$. XPS data also suggests that AlN is likely to perform better than Al2O3 as an IL for further reduction of $\mathrm{D}_{it}$ at the GeSn gate stack interface.