Session 25 overview: Clock generation for high-speed links: Wireline subcommittee

Abstract

Clock generation circuits are ubiquitous building blocks in all electronic systems and are the fundamental performance limiters in many of them. This session covers the latest advances in clock generation for high-speed links. The first paper addresses a precision quadrature generator in the latest CMOS process, making use of injection-locking techniques. The second paper presents a technique for generating high-frequency reference clocks by quadrupling the frequency of commonly used, low-cost, crystal oscillators. The third paper demonstrates a fractional PLL that uses reference clock dithering and calibrated dither cancellation in the feedback loop to effectively attenuate fractional spurs. And the final paper describes a digital ring PLL that uses a fast phase correction method and proportional pulse calibration to reduce jitter.