Package Qualification Envelope for 22FDX® Technology

C. Klewer, F. Kuechenmeister, J. Paul, D. Breuer, B. Boehme, J. Cho, S. Capecchi, Michael Thiele
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Abstract

This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.
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22FDX®技术的封装认证信封
本文描述了用于推导22FDX®完全耗尽绝缘体上硅(FDSOI)芯片封装相互作用(CPI)鉴定包络的方法。在第一部分中,讨论了各个细分市场如何影响技术特性和产品,包括BEOL堆栈和包类型。下面,总结和解释了BEOL堆叠、模具和封装尺寸的选择标准以及认证信封的互连类型。介绍了CPI的三个鉴定阶段及相关表征方法。报告了包络中使用的CPI测试结构,并在倒装芯片TQV的基础上概述了它们在技术鉴定载体(TQV)上的位置。最后,本文介绍了通过22FDX®封装和板级可靠性结果,用于线键、倒装芯片以及晶圆级扇入和扇出封装技术。报告个人资格的关键方面。
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