{"title":"A Tow-Level Buffered SDRAM Controller","authors":"T. Jin, Wenxin Li, Xiangyu Hu","doi":"10.1109/ICISCE.2016.37","DOIUrl":null,"url":null,"abstract":"With the improvement of processor and SDRAM performance, the performance of SDRAM controller becomes the bottleneck of the system performance. In this paper, a Tow-Level Buffered SDRAM controller is proposed, and its design and verification are described. To some extent, the controller improves the throughput of the processor for the SDRAM memory, and provides a solution for the design of high performance system.","PeriodicalId":6882,"journal":{"name":"2016 3rd International Conference on Information Science and Control Engineering (ICISCE)","volume":"1 1","pages":"126-128"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 3rd International Conference on Information Science and Control Engineering (ICISCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICISCE.2016.37","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
With the improvement of processor and SDRAM performance, the performance of SDRAM controller becomes the bottleneck of the system performance. In this paper, a Tow-Level Buffered SDRAM controller is proposed, and its design and verification are described. To some extent, the controller improves the throughput of the processor for the SDRAM memory, and provides a solution for the design of high performance system.
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