Kirkendall Voids Improvement in Thin Small No Lead Package

Copper Pillar bump Flipchip in the key solution in providing the breakthrough in package size reduction, lower cost package and better product performance. However there are challenges in creating a reliable copper pillar bump. Proper choice of electroplating materials and process are critical in meeting the design goals, quality and reliability. During a qualification run on a copper pillar bump flipchip on a thin small no lead package, excessive Kirkendall voids growth was found in the copper and SnAg (Tin-sliver) layer after 1000 hours of High Temperature storage at 150 deg C and 1000 cycles temperature cycle from −55°C to 150°. Methodologies like 8D, fishbone diagram and 5 why are used to investigate the root cause of this abnormality formation and deriving a robust solution to resolve the issue. The Investigation include evaluation of 2 different plating chemical and the plating parameter optimization with some improvement on the current copper pillar bump stack up. The evaluation will further validate by HTSL 175 deg C for 168 hours and X-ray and X-sectional analysis of packages.