Parallelism and pipelining in ultra low voltage digital circuits

We investigate two important performance-enhancing techniques - pipelining and parallelism - in the context of ultra-low voltage digital circuits. The investigation at near and sub-Vt supply voltages shows that pipelining can provide a superior benefit in throughput and energy-efficiency across a wide range of near and sub-Vt supply voltages while parallelism can provide a less amount of benefits only if the utilization of the circuits is high. Based on this investigation, an FFT core has been designed employing (1) an extensive degree of pipelining and (2) the parallelism with maximal utilization in major building blocks. The developed core demonstrates a significant amount of improvement in energy-efficiency and throughput over the existing near/sub-Vt FFT demonstrations.